Kontron SMARC-sAT30 Manual do Utilizador descarregar pdf (Página 33)

User’s Guide

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EDGE

FINGER

(J3)

3.2.15

Gigabit Ethernet Controller (GbE) Interface

The SMARC sAT30 module supports one GbE interface. This is accomplished by using the Intel I210 (Springville) GbE

MAC+PHY using one of the T30 SoC’s PCIe interfaces. This is diagrammed below. The PCIe coupling caps are not shown

in the diagram.

AH25

AJ25

AG23

AG22

GBE_PCIE_TX_P

GBE_PCIE_TX_N

GBE_PCIE_RX_P

GBE_PCIE_RX_N

GBE_PCIE_CLK_P

GBE

GBE_MDI0_P

GBE_MDI0_N

GBE_MDI1_P

GBE_MDI1_N

GBE_MDI2_P

GBE_MDI2_N

GBE_MDI3_P

P30

P29

P27

P26

P24

P23

T30 CPU

(U10)

AJ27

AH27

GBE_PCIE_CLK_N

CONTROLLER

INTEL I210

(U27)

GBE_MDI3_N

P20

P19

AG25

GBE_PCIE_RST#

GBE_LINK100#

GBE_LINK1000#

GBE_LINK_ACT#

P21

P22

P25

GBE_PCIE_DIS#

PCIE_WAKE#

S146

Figure 6 GbE Controller Implementation

The following table details the Tegra to I210 connection details.

NVIDIA T30 CPU

Intel I210

Net Name

Notes

Pin #

Pin Name

Pin #

Pin Name

AH25

PEX_L5_TXP

PE_RX+

GbE_PCIE_TX_P

Differential PCIe GbE transmit data

pair

AJ25

PEX_L5_TXN

PE_RX-

GbE_PCIE_TX_N

AG23

PEX_L5_RXP

PE_TX+

GbE_PCIE_RX_P

Differential PCIe GbE receive data pair

AG22

PEX_L5_RXN

PE_TX-

GbE_PCIE_RX_N

AJ27

PEX_CLK3P

PECLK+

GbE_PCIE_CLK_P

Differential PCIe GbE reference clock

AH27

PEX_CLK3N

PECLK-

GbE_PCIE_CLK_N

AG25

PEX_L2_RST#

PE_RST#

GbE_PCIE_RST#

PCIe GbE reset input

GMI_AD14

SDP1

GbE_PCIE_DIS#

INTEL I210 PCIe interface disable

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 83 84

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