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COM Express Interfaces
pin will be read high. Software then uses this information to apply power to the card. There is no
standard input port pin defined by COM Express for this function. For systems that are not trying
to implement hot-swap capability, it is not necessary to be able to read back the state of the
PRSNT2# pin. Hence it is shown in the figure above as being brought to a test point.
Nets SMB_CK_S0 and SMB_DAT_S0 are sourced from COM Express Module pins B13 and B14
respectively. _S0 version of SMBUS needs to be FET isolated from Module version which is on
the _S5 power rail. The SMBUS supports card-management support functions. SMBUS
software can save the state of the slot-card device before a Suspend event, report errors, accept
control parameters, return status information and card information such as a serial number.
Support for the SMBUS is optional on the slot card. Please refer to chapter 2.19 'System
Management Bus (SMBus)' on page 123 below for more information on SMBUS.
WAKE0# is asserted by the slot card to cause COM Express Module wake-up at Module pin B66.
This is an open-drain signal. It is an input to the Module and is pulled up on the Module. Other
WAKE0# sources may pull this line low; it is a shared line.
Slot JTAG pins on A5-A8 are not used.
2.3.5.4. x4 Slot Example
Figure 8: PCI Express x4 Slot Example
PICMG
®
COM Express
®
Carrier Board Design Guide Rev. 2.0 / December 6, 2013
38/218
VCC_12V VCC_12V
VCC_3V3
VCC_3V3_SBY
VCC_3V3
VCC_3V3
CEX
PCIE_TX0+
CEX
PCIE_RX0+
CEX
PCIE_TX0-
CEX
PCIE_TX1+
CEX
PCIE_TX1-
CEX
PCIE_TX2- CEX
PCIE_TX2+
CEX
PCIE_TX3- CEX
PCIE_TX3+
CEX
PCIE_RX0-
CEX
PCIE_RX1-
CEX
PCIE_RX1+
CEX
PCIE_RX2-
CEX
PCIE_RX2+
CEX
PCIE_RX3+
CEX
PCIE_RX3-
SMB_CK_S0
SMB_DAT_S0
CEX
WAKE0#
PCIE_RESET1#
PCIE_CLK_REF0+
PCIE_CLK_REF0-
0R
R16
R17
4.7k
TP2
Do Not Stuff
J2J2
PCIe x4 Slot
+12V
B1
+12V
B2
+12V
B3
GND
B4
SMCLK
B5
SMDAT
B6
GND
B7
+3.3V
B8
JTAG1
B9
3.3VAUX
B10
WAKE#
B11
PRSNT1#
A1
+12V
A2
+12V
A3
GND
A4
JTAG2
A5
JTAG3
A6
JTAG4
A7
JTAG5
A8
+3.3V
A9
+3.3V
A10
PERST#
A11
RSVD
B12
GND
B13
PETp0
B14
PETn0
B15
GND
B16
PRSNT2#
B17
GND
B18
PETp1
B19
PETn1
B20
GND
B21
GND
B22
PETp2
B23
PETn2
B24
GND
B25
GND
B26
PETp3
B27
PETn3
B28
GND
B29
RSVD
B30
PRSNT2#
B31
GND
B32
GND
A12
REFCLK+
A13
REFCLK-
A14
GND
A15
PERp0
A16
PERn0
A17
GND
A18
RSVD
A19
GND
A20
PERp1
A21
PERn1
A22
GND
A23
GND
A24
PERp2
A25
PERn2
A26
GND
A27
GND
A28
PERp3
A29
PERn3
A30
GND
A31
RSVD
A32
X1
X1
X2
X2
- COM Express® 1
- Carrier Design Guide 1
- Contents 3
- 1. Preface 8
- 1.6. Name and logo usage 9
- 1.7. Intellectual property 10
- Term Description 11
- 1.10. Schematic Conventions 15
- 2. COM Express Interfaces 16
- COM Expre ss Module 17
- Type 10 17
- Table 4: Pin-out Comparison 20
- , the PCI 30
- 2.3.5. Schematic Examples 34
- Signal Pin Description I/O 45
- Figure 15: ExpressCard Size 45
- 2.4.1. Signal Definitions 48
- 2.4.2. PEG Configuration 49
- 2.4.3. Reference Schematics 52
- DisplayPort is supported 55
- DisplayPort Example 56
- Figure 21: HDMI Example 57
- Figure 22: DVI Example 59
- SDVO Port Configuration 61
- Supported SDVO Devices 62
- DVI_SDAROM 63
- DVI_SCLROM 63
- SDVO I2C Bus Address 63
- Write = 0111 0000 (70h) 63
- Read = 0111 0001 (71h) 63
- 2.6.1. Signal Definitions 66
- Earliest asserted 1ms after 68
- 3.3V, 5V and 12V are stable 68
- 2.7. LAN 70
- 2.7.2. Reference Schematics 73
- 2.8. USB Ports 76
- 2.8.2. Reference Schematics 77
- 2.9. USB 3.0 81
- 2.9.1.3. USB 3.0 connector 83
- 2.9.2. Reference Schematics 84
- 2.10. SATA 87
- Pins Signal Description 88
- SATA Port 89
- 2.11. LVDS 91
- Term Definition 94
- 2.11.2. Reference Schematics 97
- 2.12.1. Signal Definitions 99
- 2.12.2. Reference Schematics 100
- 2.13. VGA 101
- COM Express Interfaces 102
- 2.14. TV-Out 104
- COM Express Module 106
- AUDIO POWER 107
- AUDIO CODEC - ALC888 107
- ANALOG I/O CONNECTOR 107
- 2.15.1.2. AC'97 108
- Figure 41: Audio Amplifier 109
- 2.16.1. Signal Definition 111
- SUPER I/O 115
- COM1/COM2 116
- 2.17.1. Signal Definition 118
- 2.18.1. Signal Definitions 121
- 2.18.2. Reference Schematics 121
- 2.19.1. Signal Definitions 123
- 2.20.1. Signal Definitions 125
- C O M 1 C O M 2 126
- 2.21. CAN Interface 127
- 2.21.2. Reference Schematics 128
- 2.22. Miscellaneous Signals 129
- POWER ATX 133
- POWER AT 133
- Type 2 Detection 133
- 2.22.5. Watchdog Timer 137
- G P IO C o n n e c t o r 141
- 2.22.8. Fan Connector 142
- 2.22.9. Thermal Interface 143
- 2.23. PCI Bus 147
- 2.23.2. Reference Schematics 148
- 2.24.1. Signal Definitions 153
- 3. Power and Reset 156
- 3.2.1. ATX vs AT Supplies 157
- 3.2.2. Power States 157
- Power and Reset 158
- 3.2.5. Power Button 162
- 3.4. Reference Schematics 164
- Table 55: ATX Signal Names 166
- ATX Signal Name Description 166
- 3.5. Routing Considerations 167
- 3.5.3. VCC5_SBY Routing 168
- 4. BIOS Considerations 170
- Type Height Partnumber Note 171
- COM Express Module Connectors 172
- GND Plane 173
- Power Plane 173
- COM Express 175
- Table 60: Trace Parameters 176
- Symbol Definition 176
- Carrier Board 178
- Parameter Trace Routing 183
- Extended 194
- 7.2. Heatspreader 195
- (Ø2.7mm bore hole) 196
- (M2.5 thread) 196
- (Ø2.7 bore hole) 197
- Mechanical Considerations 198
- 8.3. Useful books 202
- 9.1. TV-Out 203
- 9.1.5. Signal Termination 206
- 9.1.6. Video Filter 206
- 9.1.7. ESD Protection 206
- 9.2. LPC Firmware Hub 207
- Appendix C: List of Tables 213
- Appendix D: List of Figures 215
- Table 79: Revision History 217
- Revision Date Author Changes 217
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